Principal Analog and Mixed-Signal Circuit Designer
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You are a passionate and experienced Analog and Mixed-Signal Design Engineer with a strong background in CMOS analog and mixed-signal circuit design. You thrive on tackling complex challenges and are excited about the opportunity to work on cutting-edge PLL designs that will power the next generation of datacenters, automobiles, and communications networks. You have a keen eye for detail and excel in designing high-speed digital circuits and analog components. Your technical expertise is complemented by your ability to mentor junior designers and collaborate effectively with layout and CAD teams. With a deep understanding of PLL loop operation and design, you are ready to contribute to high-speed SerDes designs, including PCI-Express, Ethernet, and CPRI applications at rates up to 224Gbps and beyond.
You will join the PLL design team, a dedicated group of engineers focused on creating innovative designs that enable the next generation of high-speed communication systems. Our team collaborates closely with various departments, including layout and CAD teams, to ensure the successful delivery of high-performance PLLs and SerDes designs. We value creativity, technical excellence, and a collaborative spirit, and we are committed to pushing the boundaries of what is possible in analog and mixed-signal design.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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